i was looking at some of the nes schematics and was looking to see how the ppu resisters are connected to the ppu from the cpu. how does the cpu access the ppu ? is the address bus and data bus connected for that time ?
matt
The CPU writes to PPU memory through a set of four ports: $2003 for OAM address, $2004 for OAM data, $2006 for VRAM address, and $2007 for VRAM data. A program will seek to a PPU address through one register and then write to that address (and following addresses) through the other register of the pair. Have you read
NESdevWiki:NES PPU yet?
that didnt explain how the cpu is connected to the ppu. if the cpu reads/writes to a ppu register through the memory, sets an address on the bus, what what on the ppu listens to that address ? are the cpu and ppu address lines connected when a memory mapped register is used? are the cpu and ppu data lines connected when a memory mapped register is used ?
The PPU has D0-D7+A0-A2+M2+R/W inputs, as well as a register select signal. These are connected straight to the NES CPU (except for the register select signal, which goes through a selector to be enabled only for $2000-$3FFF).