PPU Rendering Pipeline

This is an archive of a topic from NESdev BBS, taken in mid-October 2019 before a server upgrade.
View original topic

PPU Rendering Pipeline
by zeroone on 2015-08-22 (#153784)

In attempt to improve the accuracy of my PPU implementation, I have been studying the source code of Nintendulator (PPU.cpp). I noticed that VRAM reads and writes are delayed by 3 PPU cycles:

Code:

unsigned char IOVal;
unsigned char IOMode;   // Start at 6 for writes, 5 for reads - counts down and eventually hits zero

...

IOMode -= 2;

Is the delay related to the PPU rendering pipeline?

Re: PPU Rendering Pipeline
by Drew Sebastino on 2015-08-22 (#153787)

I'm sorry if I'm derailing this thread when it just started, but what is a "pipeline" in electronics? I've been itching to ask this.

Re: PPU Rendering Pipeline
by rainwarrior on 2015-08-22 (#153790)

A pipeline is a series of operations done in sequence. This usually implies that they are done independently as well, so you can have multiple items proceeding along the pipeline at the same time, each one in a different stage.

This may help: http://en.wikipedia.org/wiki/Pipeline_(computing)

Re: PPU Rendering Pipeline
by Drag on 2015-08-23 (#153835)

It takes the PPU 2 cycles to output a full 14-bit address, so that's why accesses are delayed like that. I think the third cycle in that delay is because the CPU can initiate a fetch while the PPU is on the second of its two-cycle procedure for outputting an address, which would mean the fetch would take 3 PPU cycles to complete, instead of 2. Someone may need to fact check me on that though.