Simple question actually. Should the effects of a processor cycle be immediate or when the cycle ends (which is a 3 pixel difference). For example
INC Instruction (Absolute addressing):
Cycle 1: Fetch Opcode
Cycle 2: Fetch Low Byte of Address
Cycle 3: Fetch High Byte of Address
Cycle 4: Read from Address
Cycle 5: Write old value back to Address
Cycle 6: Write new value back to Address
So let's pretend the address is 2007, the bastards. What I'm saying is should the write take effect on the PPU in ppu cycle 12 or ppu cycle 15?
I.E. Should 12 pixels be rendered before the write takes effect or 15?
To me it seems like it should be 15, since the ppu shouldn't know the write to that memory location occurred until the processor cycle has completely finished...however some people have spoken of otherwise...
It could be something freaky like MID-CYCLE! AHHHH
Thanks
INC Instruction (Absolute addressing):
Cycle 1: Fetch Opcode
Cycle 2: Fetch Low Byte of Address
Cycle 3: Fetch High Byte of Address
Cycle 4: Read from Address
Cycle 5: Write old value back to Address
Cycle 6: Write new value back to Address
So let's pretend the address is 2007, the bastards. What I'm saying is should the write take effect on the PPU in ppu cycle 12 or ppu cycle 15?
I.E. Should 12 pixels be rendered before the write takes effect or 15?
To me it seems like it should be 15, since the ppu shouldn't know the write to that memory location occurred until the processor cycle has completely finished...however some people have spoken of otherwise...
It could be something freaky like MID-CYCLE! AHHHH
Thanks