According to the wiki, "Reading/Writing to $5000 or $5800 will acknowledge any pending IRQs." However, I suspect that only writing to those registers will ack the IRQ. Namco Classic (Japan) continually polls (reads) from those registers on the screen where the player swings at the ball. Meaning, the interrupt request line will be pulled low when the timer expires and then it will immediately be restored to high during a register read. I don't know if the processor latches such a brief movement, but it sounds like an interrupt could be missed. For instance, a branch instruction supposedly is capable of delaying an interrupt by 1 instruction. The subsequent instruction could poll the register, raising the IRQ line. Consequentially, could the processor not handle the IRQ entirely?
Even if that situation is impossible, it seems suspiciously odd that the code would be written to poll the registers, causing continuous IRQ acks, instead of only acknowledging IRQ after it happens.
Even if that situation is impossible, it seems suspiciously odd that the code would be written to poll the registers, causing continuous IRQ acks, instead of only acknowledging IRQ after it happens.