a simple mmc3 counter question

a simple mmc3 counter question
by Anes on 2006-02-26 (#10146)

What does $C001 does, clear directly the IRQ counter, and with clearing i mean does it set it to "0"? or on the next rising edge of A12 will set it to "0".
So if a few words:

- kevtris means "clear" to set it to "0"?
- when $C001 is written the counter is affected directly? (cos kevtris says that that there is no direct access)

thxs in advance.

by Quietust on 2006-02-27 (#10151)

1. If the IRQ counter is zero when gets clocked, it will reload its value from the IRQ latch.
2. If you write to $C001, then on the next clock the IRQ counter will reload its value from the IRQ latch.

Writing to $C001 effectively zeroes out the IRQ counter, since it causes it to reload on the next clock. The fact that IRQs get generated when the counter makes a transition to zero isn't a problem, since IRQs are only generated when the counter is clocked.

Alternately, you can simply think of the "Reload IRQ counter from latch instead of decrementing it" signal has having two inputs: "IRQ counter is zero" and "Wrote to $C001". The end effect is the same.

by Anes on 2006-02-27 (#10162)

thanks quietust.

by darklink on 2006-05-20 (#13126)

so does it means that if latch contain 0,
then it is functionnaly same as irq disabled because no transition from non-0 to 0?

I have some questions in more detail,
does the irq part work as follow(or functionlly same) ?:

on reset, irq disabled, clear irq pending. and irq latch and irq counter both contain 0.

when irq counter is written($c000), it count from this value in next clock. what happen if 0 is written and then clocked ? just reload from latch and NOT generate irq ?
when irq latch is written($c001), it update the counter from latch in next clock. this is the same as put 0 in counter (if the assumption above is correct).
when disabled($e000), copy latch value to counter.(so when enabled, it will decrement in the 1st clock rather than get it from latch).
when enabled($e001), no change to latch or counter.

if irq is enabled:
when PPU A12 change from 0 to 1(or 1 to 0?) 42 times (is that means there is a 42-divider?), irq counter is clocked once. and what happen after the clock is what asked above.

and more questions if there is a 42-divider( please don't bother about me :
when latch is update, is this divider reset?
when irq is enabled or disabled, what happen to this divider?