Can somebody explain me this?? (ntsc and spr 0)

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Can somebody explain me this?? (ntsc and spr 0)
by Anes on 2014-09-07 (#133669)
The "Notes" Section of the "Ppu Clock Diagram Picture" says:

Code:
Sprite zero act as if the visible image starts at h = 2 (i.e., the
sprite 0 hit flag will be set during the third tick of a scanline at the earliest).
Actual pixel output is delayed by two or more ticks, so the first pixel of a
scanline is output at h = 4 (due to the way the internal render pipeline is
set up, with palette lookup taking place after the tile and attribute bits
are fetched)


My sprite 0 hit is raised in the multiplexer when a Non transparent Bg Pixel and a Non transparent Sprite Pixel joins together.
I really don't understand it...
Re: Can somebody explain me this?? (ntsc and spr 0)
by tepples on 2014-09-07 (#133672)
I take it to mean that the PPU is pipelined. Each step in rendering a pixel takes time for the circuit to settle, which means each stage processes the output from the previous stage a pixel ago.
  1. Background and sprite pixels are shifted out and combined with attribute bits.
  2. The frontmost background pixel and the frontmost sprite pixel are combined in the multiplexer. Sprite 0 hit is evaluated here.
  3. Pixels are looked up in the palette.
  4. Values from the palette are sent to the composite signal generator. Emphasis bits are combined here.