NMI question

Two 1-bit registers inside the PPU control the generation of NMI signals. Frame timing and accesses to the PPU's PPUCTRL ($2000) and PPUSTATUS ($2002) registers change these registers as follows, regardless of whether rendering is enabled:
1.Start of vertical blanking: Set NMI_occurred in PPU to true.
2.End of vertical blanking, sometime in pre-render scanline: Set NMI_occurred to false.
3.Read $2002: Return old status of NMI_occurred in bit 7, then set NMI_occurred to false.
4.Write to $2000: Set NMI_output to bit 7.

The PPU pulls /NMI low if and only if both NMI_occurred and NMI_output are true. By toggling NMI_output ($2000 bit 7) during vertical blank without reading $2002, a program can cause /NMI to be pulled low multiple times, causing multiple NMIs to be generated.

data ReadPpuMem(addr)
{

    switch (addr)
    {
     //other cases...
     case 2002:
         //other things here
         data |= Ppu.on_vblank;
         Ppu.on_vblank = 0;
         break;
    }
    return data;
}

data ReadPpuMem(addr)
{

    switch (addr)
    {
     //other cases...
     case 2002:
         //other things here
         data |= Ppu.on_vblank;
         Ppu.on_vblank = 0;
         
         //new code
         if (Ppu.scanline == 241 && Ppu.scanline_cycle == 1)
              Ppu.cant_setvblank = 1; 

       break;
    }
    return data;
}

...
if (Ppu.scanline == 241 && Ppu.scanline_cycle == 1)
    if (!Ppu.cant_setvblank)
        Ppu.on_vbank = 0x80;
    else
        Ppu.cant_setvblank = 0;
...

      case 0:
        if( (ppu->reg0 & 0x80) && !(data & 0x80) )
        {
           cpu_nmicancel();
        }
        else if( !(ppu->reg0 & 0x80) &&  (data & 0x80) && (ppu->status & 0x80) && (341 != ppucycle))
        {
           cpu_nmitrigger();
        }