koitsu wrote:
Markfrizb wrote:
http://youtu.be/5QefJWQ12u4
Sorry for the semi-off-topic question relating to hardware, but: I've always been curious how that "stacking" of chips actually works. It looks like you've got two flash chips on small PCBs (presumably that's the TSOP stuff?) stacked atop one another before being soldered to the mainboard. How exactly does the underlying hardware work with that, e.g. say both chips were 8mbit, how given that configuration would one be able to access the first chip vs. the second, especially if they share the same pins?
This isn't the only place I've seen this done; I've seen commercial motherboards or random consumer products where literally two DRAM or flash chips are stacked on top of one another before being soldered to the board, but I have no idea how this actually manages to work.
Mark already covered this pretty well, but I'd also like to mention that this is basically exactly how boards with 2 ROM chips or even ROM + SRAM work, but they just use board traces to connect instead of stacking. The thing is, when you use 2 identical chips, all of the pins that you want to connect together just so happen to be in the same place, so you can stack them in order to connect them. They share the same exact address and data bus, the only difference is the chip select pin (or sometimes the output enable is used instead, Nintendo seemed to swap /CS and /OE whenever they felt like it because it really didn't matter for MaskROMs). You do have to lift the chip select pin on the top ROM, because (as the name suggests), that's how you select which chip actually drives the data bus. So that's the part you probably missed in seeing all of the other pins connected together. The chip select signal is still separate for each chip, which are then connected separately to the mapper.
The way memory-mapped I/O works from a hardware perspective is that you have a shared address and data bus for all of the chips, then you have 3 control signals, write enable (/WE), output enable (/OE, you can also think of this as a read enable, in contrast to write enable), and chip enable (/CE, aka chip select, /CS). Sometimes you will also see a CE2 on SRAM, but what that actually does is that you tie it to the Vcc rail through a pull-up resistor and it disables the chip until the voltage rail is stable, so while it is a secondary chip enable, you would not use it as a chip
select. It's sometimes referred to as /RST instead. /OE and /WE can be connected between all of the chips on the board if you want, but you need a separate /CE for each one. If you want to read from a chip, you set the address bus, pull /CE low on the specific chip you want to read from, then pull /OE low and /WE high to indicate a read, at which point (after a propagation delay) you can read the data off the data bus. A write is similar, set up the address, set up the data bus, pull /CE low on the chip, then /WE low and /OE high. Any chip with /CE high simply doesn't respond to the /OE and /WE signals, so that's why it's ok for those two to be shared, and it's why you don't get bus conflicts despite all the different chips on the board (assuming everything is working correctly, and also it's worth noting that this is the same bus used internally by everything inside the console as well, the cart slot is just an extension of that bus). So now, you have multiple chips on one board and you want them to be mapped to certain address ranges. That's where the mapper comes in. It basically just taps into the address lines, and then based on what address you put on the address bus, it selects the proper chip and sets the /CE outputs properly.
Glad you like them.
. But on the other hand, it is very good as a testing board and I'm really impressed it supports literally everything, including all LO/HIRom games (even Star Ocean) and even multicarts on the same board.... just wow, I'm speechless