Hi all, I've been working on a new Toshiba TLCS900/H CPU core for a new Neo Geo Pocket (+Color) emulator, but I'm having some trouble finding good information on instruction timings.
There doesn't appear to be timing information, at least not understandable to me, in the official documentation.
(Google search for "tlcs900/h1 pdf", second link.)
I found these old threads:
* https://forums.nesdev.com/viewtopic.php?f=23&t=10026
* https://forums.nesdev.com/viewtopic.php?f=23&t=9383
But the information doesn't seem complete.
All the cores based around NeoPop has entire instruction cycle counts, but I don't know where they came from, and it would seem most people online agree the timing of these emulators isn't so great, so I'd like to do better if possible.
Can anyone point me at some better documentation?
While I'm at it, I'm guessing I'm not going to get any test ROMs to debug my TLCS900/H core ... ^-^;;
That's going to be really rough ... this CPU ended up being more complex (and more code) than my M68K core.
For whatever it's worth, in case anyone is feeling super generous about helping ...
Current code is here: https://gitlab.com/higan/higan/tree/mas ... r/tlcs900h
But wait for v106r83 in day or so to land, as I fixed LDA and one instruction that was taking a (#8) instead of (#16).
Thanks in advance! :D
There doesn't appear to be timing information, at least not understandable to me, in the official documentation.
(Google search for "tlcs900/h1 pdf", second link.)
I found these old threads:
* https://forums.nesdev.com/viewtopic.php?f=23&t=10026
* https://forums.nesdev.com/viewtopic.php?f=23&t=9383
But the information doesn't seem complete.
All the cores based around NeoPop has entire instruction cycle counts, but I don't know where they came from, and it would seem most people online agree the timing of these emulators isn't so great, so I'd like to do better if possible.
Can anyone point me at some better documentation?
While I'm at it, I'm guessing I'm not going to get any test ROMs to debug my TLCS900/H core ... ^-^;;
That's going to be really rough ... this CPU ended up being more complex (and more code) than my M68K core.
For whatever it's worth, in case anyone is feeling super generous about helping ...
Current code is here: https://gitlab.com/higan/higan/tree/mas ... r/tlcs900h
But wait for v106r83 in day or so to land, as I fixed LDA and one instruction that was taking a (#8) instead of (#16).
Thanks in advance! :D