byuu wrote:
Sorry, didn't notice this sooner. Don't usually frequent this subforum.
(That and I lost a week learning about X509 certificates. Those things are horrifically complex.)
Greatly appreciate the info!! Glad to have gotten it now before I went too far into writing the core.
I scrapped what I had and started over to support the T-cycles properly (including the extra clock for opcode fetches), as well as to handle the way you can stack DD/FD opcode prefix flags; and to roll them into the regular tables, so that there's only three now (main, CB, ED.)
This CPU is certainly a lot less awful to emulate than the 68K, but it's still not very fun >_>
Just out of curiosity, does anyone know the bus hold delays for the various read/write/in/out operations on the Z80?
Eg is it:
* wait 4 clocks
* read from in
* return in value
Or more like:
* wait 2 clocks
* read from in
* wait 2 clocks
* retur in value
If we have no idea, then I'll just guess something for the time being.
You know that memory accesses aren't instantaneous but consist of a sequence of operations, right? The timing for every signal for every type of cycle (fetch, read, write, in, out) is shown starting on page 13 of the Zilog manual (page 33 of the PDF).
The important takeaway is that opcode fetches are compressed into just 2 clocks; the second 2 clocks of an M1 cycle are DRAM refresh, in which the Z80 puts the contents of the R register on the address bus and then increments the lower 7 bits of R (you probably don't have to emulate the refresh itself, but you do need to emulate the R register because software can read it; it's sometimes used by games as a PRNG seed)
I think what you really want to know is "if the Z80 does a read/write that triggers an interrupt from some device, does the device respond fast enough to interrupt the Z80 before it starts the next instruction?" And that depends on the hardware responding to the write (e.g. the VDP), so you'll have to consult Sega-specific documentation.
byuu, on twitter wrote:
Why does [inc (hl)] take 11 cycles?
Memory RMW operations on the Z80 have one internal operation between the read and the write for the same reason they do on the 6502: it takes time to actually do the inc/dec/shift/whatever. Like I said, the Z80 manual shows most IOs as part of the preceding memory cycle (which they are from the perspective of the chip's microcode, I guess). The exact breakdown of that instruction for bus timing purposes is:
fetch/decode opcode (2+2 clocks)
read memory (3 clocks)
internal operation (1 clock)
write memory (3 clocks)
Every place the manual shows a memory read taking more than 3 clocks, or an opcode fetch/decode taking more than 4 clocks, it should be interpreted as "standard read or fetch cycle with (n - 3) or (n - 4) internal operations after".