Hey guys,
I'm having issues when I try to run data signals through my CPLD. If I run the data lines directly from the ROM to the cart edge they work fine, but when running them to the CPLD and having the data input buffered directly to the data output THROUGH the CPLD, either with vhdl or schematic design, the cart stops working. Address lines work properly through the CPLD using the same methods, though.
Is there something that I need to do for handling data signals, as compared to address signals? I'm assuming it's because they're bi-directional, and I've got bi-directional buffers on them, but it makes no difference.
Digital voltage logic thresholds, maybe?
e.g. the SNES is 5V CMOS, and requires voltages above 4V and below 1V to reliably read as digital 1 and digital 0.
The NES is 5V NMOS, and instead has TTL voltage thresholds (above ~2.5V and below 1V)
lidnariq wrote:
Digital voltage logic thresholds, maybe?
How would this differ in an FPGA? I looked at my SD2SNES cart and all the pins from the RAM on there run to the FPGA, which tells me that it can be done, at least on an FPGA. I was wondering if this could be timing related because FPGA chips tend to have faster response times than a CPLD, but I'm not 100% sure.
The FPGA on the sd2snes almost certainly has some voltage translation to make it compliant with the SNES's different signalling voltages.
What voltage are you running the CPLD at?
This is running in a 3V system using a 3V CPLD (XC95144XL). So voltage translation isn't required.
Oh. Well. I don't suppose you happen to have an oscilloscope?
lidnariq wrote:
Oh. Well. I don't suppose you happen to have an oscilloscope?
No, and I don't have access to one either unfortunately.
Um. Random guess: are you tristating the data lines at the correct times?
I was just setting this up as straight through-put.
So in vhdl the part where I assign data_out looks like this:
data_out (15 downto 0) <= data_in (15 downto 0);
In schematic entry it was a 16 bit buffer, nothing more. I literally just want the signals to pass through the CPLD for PCB routing purposes.
Is the ROM always supposed to drive the data bus? It's not shared with anything else?
The data bus is shared with at least WRAM, PPU registers, APU registers, battery RAM in the cartridge (if any), and the coprocessor (if any).
This isn't a SNES or NES; he said it's some 3V system.
lidnariq wrote:
Is the ROM always supposed to drive the data bus? It's not shared with anything else?
Yes the ROM is the only thing on that bus. That's why it's been stumping me, because there really is nothing in the way of it except the CPLD.
I guess I'll just play with it some more