[OVERVIEW]
I successed digital video outputs for PCEngine. It uses real hardware, no modification, no AD converter.
CD excluded PCEngine system has EXTBUS. It contains full CPU buses and dotclock and color RAM address bus(VDC data).
I've researched them, EXTBUS outputs perfectlly digital video data before DA convert by VCE(6260).
I designed interface the PCB between EXTBUS and Terastic's Cyclone V development board(c5g).
The FPGA watches write cycles for VCE register, stores VDC data into internal RAM, outputs upscanned digital video to T.M.D.S encoder.
[Destinaion Display resolution]
VCE divides master clock as dotclock, the divide numbers 4, 3 or 2. Digital video needs fixed number multiply for the upscan. I design scanline multiply number is 3. The resolution are XGA (1024x768) and 720p (1280x720). It is async outputs, FPGA uses single frame buffer, the tearing happens about every 6 seconds. The player dont mind the tearing, it is the ideal spec...
I have tried full sync digital video output. I have not successed, it maybe requires modify to output master clock into external side. If FPGA gets PCE master clock, it can outputs stable T.M.D.S waveform, the LCD monitor won't display clarity. Because the video signal is non-compliant XGA. Full synced pixel clock is 21.47*3MHz, XGA requies 65.0MHz.
[confirmed software]
I checked about 30 HuCard games. Almost ganes works with clarirty video.
[next]
I will implement the backup memory system into the C5G.
(edit) added new photo.
- R-TYPE part2 (dotclock = master /3)
- TV sports bascketball (dotclock = master /2)
- Momotarou Densetsu Gaiden (dotclock = master /4)
I successed digital video outputs for PCEngine. It uses real hardware, no modification, no AD converter.
CD excluded PCEngine system has EXTBUS. It contains full CPU buses and dotclock and color RAM address bus(VDC data).
I've researched them, EXTBUS outputs perfectlly digital video data before DA convert by VCE(6260).
I designed interface the PCB between EXTBUS and Terastic's Cyclone V development board(c5g).
The FPGA watches write cycles for VCE register, stores VDC data into internal RAM, outputs upscanned digital video to T.M.D.S encoder.
[Destinaion Display resolution]
VCE divides master clock as dotclock, the divide numbers 4, 3 or 2. Digital video needs fixed number multiply for the upscan. I design scanline multiply number is 3. The resolution are XGA (1024x768) and 720p (1280x720). It is async outputs, FPGA uses single frame buffer, the tearing happens about every 6 seconds. The player dont mind the tearing, it is the ideal spec...
I have tried full sync digital video output. I have not successed, it maybe requires modify to output master clock into external side. If FPGA gets PCE master clock, it can outputs stable T.M.D.S waveform, the LCD monitor won't display clarity. Because the video signal is non-compliant XGA. Full synced pixel clock is 21.47*3MHz, XGA requies 65.0MHz.
[confirmed software]
I checked about 30 HuCard games. Almost ganes works with clarirty video.
[next]
I will implement the backup memory system into the C5G.
(edit) added new photo.
- R-TYPE part2 (dotclock = master /3)
- TV sports bascketball (dotclock = master /2)
- Momotarou Densetsu Gaiden (dotclock = master /4)