Espozo wrote:
ARM processors use loading and storing. (I thought every processor used loading and storing and if they didn't, how could you even do anything?)
In RISC processors, the
only instructions that support a memory operand are load and store. The rest work entirely on registers and immediate values.
Quote:
Early ARM processors didn't support 8bit and 16bit instructions?
Thumb and MIPS16 were introduced because ARM and MIPS felt that their architectures' code density on binary-size-constrained architectures couldn't compete with 8- and 16-bit MCUs.
Quote:
I really have no clue as to what this is saying but I guess that it just means that you can put 16 and 32 bit instructions in the stack?
Programs use 16-bit instructions, which can't efficiently do all the things 32-bit instructions can, because it takes two reads to get a 32-bit instruction out of ROM or main RAM. But there's a fast RAM called IWRAM, normally used for the stack, where you can copy 32-bit code such as an audio mixer or a texture mapper.
Quote:
Isn't this bullet point the exact same thing as 2?
What "2"? Could you please use the quote markup if you're going to be referring to a particular point of an article? A Wikipedia article may change between the day you write your post and the day when someone else reads your post, possibly months or years later.
Quote:
This means that there's no weird 21 megahertz (I think that's the number) speed that's really only about 3.5 megahertz like the on the Super Nintendo because everything needs to have been gone over a couple times?
There's the 16.78 MHz master clock. And as on the Super NES, different memory regions have different speeds: divide by 3 cycles to read or write main RAM and 2 or 4 cycles to read ROM.
Quote:
It is saying that there is conditional instructions instead of conditional branching? Would it be like add if equal instead of branch if equal? (beq)
Yes. In 32-bit ARM instructions (but not Thumb), any instruction can have the equivalent of branch conditions on it.
Quote:
The next one says that you can easily multiply and divide 32bit instructions by 2 without much performance loss?
Yes. In 32-bit ARM instructions, you can multiply or divide one operand of each instruction by 2 as part of the same clock cycle.
Quote:
This just means it's easy to access different registers? I don't see how LDA $xxxx could be made any easier or harder.
I think "Has powerful indexed addressing modes." refers to being able to add two different registers, one with a shift amount, to form an address.
Quote:
What is a leaf instruction?
Where do you get "leaf instruction"? The Wikipedia article as of today refers to a "leaf function", which is a subroutine or function that does not call any other subroutines or functions.
Quote:
I don't know what the last one is saying but It appears to be talking about bank switching.
Nope, it's talking about having a separate set of registers to be used during interrupt handlers, so you don't have to waste time pushing the values of all registers to memory at the start of an interrupt handler and pulling them back.
Quote:
Oh, and I wonder, is there still x and y?
There are 14 numbered registers that can be used for data (like 6502 A) or address (like 6502 X and Y). The other two are reserved for the stack pointer (like 6502 S) and the program counter (like 6502 PC).
Quote:
rainwarrior wrote:
The downside, though, is that you can't use arithmetic instructions directly with memory.
could you give me an example as to what you mean?
You can't ADC with an address as an operand; you instead have to load the value from that address into memory.
I wonder if part of the problem is that forum.gbadev.org has made itself invisible to external search engines to deter spambots from finding it, registering, and posting.