Greetings,
This is my first post, so allow me to briefly introduce myself. I'm a recent grad that's currently employed in FPGA based digital hardware design. I'm a retro gamer whose childhood was practically founded on the nintendo's old systems, including, of course, the NES! As such, I've been dedicating my free time towards a personal milestone -- to make an open source FPGA based implementation of the NES. The plan is that it won't end there, but I'm taking it one step at a time. I'd like to thank all of the users and maintainers of this superb resource, and look forward to contributing in any way I can.
--- Project Details ---
overview:
I began this project about a year ago while completing my senior year in college. The project remained stagnant for the passed few months, but recently I've found enough regular free time to get it in motion again. As a side-note I am aware that there are 6502 cores out there, but I would personally rather make the endeavor myself. I feel like I owe it to the system, and it's honestly quite fun!
This project's goal is to create a FPGA based (verilog only) design that performs cycle-accurate execution of 6502 instructions.
The defining feature of this architecture is that native instructions are internally translated to microinstructions to simplify the internal logic of the FPGA. Will preserve inst. cycle count behavior, but not sure if I need to obey bus timing behavior as well yet. A nice side-effect of this is that technically any 8-bit opcode centered ISA can be translated by simply replacing the ROM contents of the translation unit. I've been spending the passed week hacking out a μISA with a software buddy of mine and have finally finished v1.0 of the μISA. Our next tasks are to start writing the translations & research the strictness of bus-timing the MMIO (we're going to be making the PPU as a VGA based interface, so my theory is that we don't need to be completely stringent to the bus-timing limits of the original NES).
As always I'd be glad to share any resources in the project and will give public access to the SVN as soon as we get it setup. In case anyone is interested, here is a link to the first revision of the μISA we've reduced the native ISA to: http://www.2shared.com/document/OUv43aN ... cture.html
This is my first post, so allow me to briefly introduce myself. I'm a recent grad that's currently employed in FPGA based digital hardware design. I'm a retro gamer whose childhood was practically founded on the nintendo's old systems, including, of course, the NES! As such, I've been dedicating my free time towards a personal milestone -- to make an open source FPGA based implementation of the NES. The plan is that it won't end there, but I'm taking it one step at a time. I'd like to thank all of the users and maintainers of this superb resource, and look forward to contributing in any way I can.
--- Project Details ---
overview:
I began this project about a year ago while completing my senior year in college. The project remained stagnant for the passed few months, but recently I've found enough regular free time to get it in motion again. As a side-note I am aware that there are 6502 cores out there, but I would personally rather make the endeavor myself. I feel like I owe it to the system, and it's honestly quite fun!
This project's goal is to create a FPGA based (verilog only) design that performs cycle-accurate execution of 6502 instructions.
The defining feature of this architecture is that native instructions are internally translated to microinstructions to simplify the internal logic of the FPGA. Will preserve inst. cycle count behavior, but not sure if I need to obey bus timing behavior as well yet. A nice side-effect of this is that technically any 8-bit opcode centered ISA can be translated by simply replacing the ROM contents of the translation unit. I've been spending the passed week hacking out a μISA with a software buddy of mine and have finally finished v1.0 of the μISA. Our next tasks are to start writing the translations & research the strictness of bus-timing the MMIO (we're going to be making the PPU as a VGA based interface, so my theory is that we don't need to be completely stringent to the bus-timing limits of the original NES).
As always I'd be glad to share any resources in the project and will give public access to the SVN as soon as we get it setup. In case anyone is interested, here is a link to the first revision of the μISA we've reduced the native ISA to: http://www.2shared.com/document/OUv43aN ... cture.html