Hi all,
One more question, using Blaargs's test roms I now have my core passing all CPU instruction tests and passes the instruction timing tests fine.
It fails on every one of the memory timing tests though. What is the impact of the mem timing being incorrect? Is it likely to cause many problems or is it something that I can worry about looking at later on.
I think I'd have to change the way I'm accessing/updating memory. Currently I just record the cycles for an op and update the timer after it's executed. Am I right in thinking that the timers would need to be updated independently based on the cycles passed to correct the memory timing?
Any hints on how I would implement it?
Thanks guys
One more question, using Blaargs's test roms I now have my core passing all CPU instruction tests and passes the instruction timing tests fine.
It fails on every one of the memory timing tests though. What is the impact of the mem timing being incorrect? Is it likely to cause many problems or is it something that I can worry about looking at later on.
I think I'd have to change the way I'm accessing/updating memory. Currently I just record the cycles for an op and update the timer after it's executed. Am I right in thinking that the timers would need to be updated independently based on the cycles passed to correct the memory timing?
Any hints on how I would implement it?
Thanks guys