I am starting to work on interrupts in my emulator, but I don't quite follow exactly what's happening.
So, let me pose an example. Let's say I have STAT IRQs enabled and both LY=LYC IRQs and mode 0 IRQs enabled, but, interrupts are disabled on the CPU side (with the DI instruction.) Let's say I enable interrupts again some time on the LYC scanline after the mode 0 interrupt would have triggered
So at scanline LY=LYC we have :
My understanding is that STAT IRQ blocking occurs in this case, and only one IRQ ultimately triggers. Is this correct?
Then, suppose instead I enable interrupts some time during mode 3, and the interrupt is short and immediately exits.
EX:
Am I correct that the Mode 0 interrupt will also trigger correctly? If so, at what point in the LYC interrupt was the STAT IRQ line de-asserted?
Finally, let's say I enable interrupts before the mode 0 interrupt triggers, but the LYC interrupt doesn't complete before the mode zero one would otherwise occur:
Does the mode 0 interrupt occur after the RETI?
I hope these questions are clear. I appreciate any responses, as I would really like to get this right before I start writing spaghetti.
So, let me pose an example. Let's say I have STAT IRQs enabled and both LY=LYC IRQs and mode 0 IRQs enabled, but, interrupts are disabled on the CPU side (with the DI instruction.) Let's say I enable interrupts again some time on the LYC scanline after the mode 0 interrupt would have triggered
So at scanline LY=LYC we have :
Code:
+----......mode 2.......-.......mode 3.........-+-..........mode 0..................EI.............
^ ^ ^
LY=LYC IRQ triggers Mode 0 Interrupt triggers Master Interrupt enable
^ ^ ^
LY=LYC IRQ triggers Mode 0 Interrupt triggers Master Interrupt enable
My understanding is that STAT IRQ blocking occurs in this case, and only one IRQ ultimately triggers. Is this correct?
Then, suppose instead I enable interrupts some time during mode 3, and the interrupt is short and immediately exits.
EX:
Code:
+----......mode 2.......-...EI........RETI.......mode 3.........-+-..........mode 0........................
^ ^ ^
LY=LYC IRQ triggers Master Interrupt enable Mode 0 Interrupt triggers
^ ^ ^
LY=LYC IRQ triggers Master Interrupt enable Mode 0 Interrupt triggers
Am I correct that the Mode 0 interrupt will also trigger correctly? If so, at what point in the LYC interrupt was the STAT IRQ line de-asserted?
Finally, let's say I enable interrupts before the mode 0 interrupt triggers, but the LYC interrupt doesn't complete before the mode zero one would otherwise occur:
Code:
+----......mode 2.......-...........mode 3....EI.....-+-...............mode 0......RETI............???......
^ ^ ^
LY=LYC IRQ triggers Master Interrupt enable Mode 0 Interrupt triggers
^ ^ ^
LY=LYC IRQ triggers Master Interrupt enable Mode 0 Interrupt triggers
Does the mode 0 interrupt occur after the RETI?
I hope these questions are clear. I appreciate any responses, as I would really like to get this right before I start writing spaghetti.