Hello, everyone
I am working on the accuracy of my emulator, now using the great tests of Mooneye GB. I am currently trying to comprehend how to pass the following 2 tests, which seem contradictory to me. I can pass either of the two, but not both.
timer/rapid_toggle
timer/tima_reload
The second test (tima_reload) checks that the occurrence of a Timer interrupt is delayed by 4 clock cycles when an overflow happens. (Explained here)
However, the first test (rapid_toggle) uses the following code to check the timing of Timer interrupt, which does not seem to comply with the above mentioned behavior and test:
I can pass this test when the delay of 4 clock cycles is not implemented, since the second "ldh (<TAC), a" will trigger a Timer increase, overflow and interrupt, all before the next line "dec bc" can happen. The value of BC is therefore correct and the test is passed.
However, if the interrupt is delayed by 4 clock cycles, it is seen by the CPU only after the "dec bc" instruction is executed, therefore having a wrong value in the BC register and failing the test.
Has anyone been able to pass these 2 tests with the same implementation? Am I missing any detail? I can mention that I currently pass all the Mooneye GB tests in the "acceptance" directory, as well as all the timer tests not related to tima or tma reload, so the overall accuracy seems to be decent.
Thank you guys, I hope somebody can shed some light in my path!
I am working on the accuracy of my emulator, now using the great tests of Mooneye GB. I am currently trying to comprehend how to pass the following 2 tests, which seem contradictory to me. I can pass either of the two, but not both.
timer/rapid_toggle
timer/tima_reload
The second test (tima_reload) checks that the occurrence of a Timer interrupt is delayed by 4 clock cycles when an overflow happens. (Explained here)
However, the first test (rapid_toggle) uses the following code to check the timing of Timer interrupt, which does not seem to comply with the above mentioned behavior and test:
Code:
- ld a, %00000100 ; Start 4096 Hz timer
ldh (<TAC), a
ld a, %00000000 ; Stop timer
ldh (<TAC), a
dec bc
ld a, c
or b
jr nz, -
ldh (<TAC), a
ld a, %00000000 ; Stop timer
ldh (<TAC), a
dec bc
ld a, c
or b
jr nz, -
I can pass this test when the delay of 4 clock cycles is not implemented, since the second "ldh (<TAC), a" will trigger a Timer increase, overflow and interrupt, all before the next line "dec bc" can happen. The value of BC is therefore correct and the test is passed.
However, if the interrupt is delayed by 4 clock cycles, it is seen by the CPU only after the "dec bc" instruction is executed, therefore having a wrong value in the BC register and failing the test.
Has anyone been able to pass these 2 tests with the same implementation? Am I missing any detail? I can mention that I currently pass all the Mooneye GB tests in the "acceptance" directory, as well as all the timer tests not related to tima or tma reload, so the overall accuracy seems to be decent.
Thank you guys, I hope somebody can shed some light in my path!