PAL APU timing - NESdev BBS

PAL APU timing
by blargg on 2006-09-25 (#17974)

I've now timed the PAL APU's DMC and noise rates, and the frame sequencer step timing. Here are some updated tests for the frame sequencer:

pal_apu_tests.zip

Code:

Noise
Rate  0 1  2  3  4  5  6   7   8   9   A   B   C    D    E    F
      ----------------------------------------------------------
NTSC  4 8 16 32 64 96 128 160 202 254 380 508 762 1016 2034 4068
PAL   4 7 14 30 60 88 118 148 188 236 354 472 708  944 1890 3778


DMC
Rate   0   1   2   3   4   5   6   7   8   9   A   B   C  D  E  F
      ------------------------------------------------------------
NTSC  428 380 340 320 286 254 226 214 190 160 142 128 106 84 72 54
PAL   398 354 316 298 276 236 210 198 176 148 132 118  98 78 66 50


Mode 0: 4-step sequence
Action      Envelopes &     Length Counter& Interrupt   Delay to next
            Linear Counter  Sweep Units     Flag        NTSC     PAL
---------------------------------------------------------------------
$4017=$00   -               -               -           7459    8315
Step 1      Clock           -               -           7456    8314
Step 2      Clock           Clock           -           7458    8312
Step 3      Clock           -               -           7458    8314
Step 4      Clock           Clock       Set if enabled  7458    8314


Mode 1: 5-step sequence
Action      Envelopes &     Length Counter& Interrupt   Delay to next
            Linear Counter  Sweep Units     Flag        NTSC     PAL
---------------------------------------------------------------------
$4017=$80   -               -               -              1       1
Step 1      Clock           Clock           -           7458    8314
Step 2      Clock           -               -           7456    8314
Step 3      Clock           Clock           -           7458    8312
Step 4      Clock           -               -           7458    8314
Step 5      -               -               -           7452    8312

Note: the IRQ flag is actually effectively set three clocks in a row, starting one clock earlier than shown.

I find it odd that the delay reductions between some steps differed between NTSC and PAL. I double-checked those to be sure it wasn't an error on my part.

Re: PAL APU timing
by Quietust on 2006-09-25 (#17975)

For convenience, the same values as above, in hexadecimal (for those of us who prefer to put hex values in our lookup tables):

Code:

Noise
Rate   0   1   2   3   4   5   6   7   8   9   A   B   C   D   E   F
      ---------------------------------------------------------------
NTSC  004 008 010 020 040 060 080 0A0 0CA 0FE 17C 1FC 2FA 3F8 7F2 FE4
PAL   004 007 00E 01E 03C 058 076 094 0BC 0EC 162 1D8 2C4 3B0 762 EC2


DMC
Rate   0   1   2   3   4   5   6   7   8   9   A   B   C   D   E   F
      ---------------------------------------------------------------
NTSC  1AC 17C 154 140 11E 0FE 0E2 0D6 0BE 0A0 08E 080 06A 054 048 036
PAL   18E 162 13C 12A 114 0EC 0D2 0C6 0B0 094 084 076 062 04E 042 032

For the record, these all appear to be consistent with previously measured values. The new frame cycle delays, however, are a different story...

by hap on 2006-09-26 (#18000)

Thanks.

by randilyn on 2006-09-30 (#18132)

Thanks for this. =)

by Lord Nightmare on 2006-10-11 (#18344)

Sticky this, please. Or put it on the wiki if it isn't already there.

Lord Nightmare

by Quietust on 2006-10-11 (#18350)

Noise frequencies are now wiki-fied. Someone else'll have to add the frame timer stuff in a way that's meaningful.

by hap on 2006-10-24 (#18804)

June 2005 NTSC document:
Quote:
Mode 1 Timing
...
Step 3
22373 Clock linear
...
Step 4
29829 (do nothing)
...
Step 0
37283 Clock linear & length
...
(29829-22373=7456, 37283-29829=7454)

New PAL document:
Quote:
Mode 1: 5-step sequence
...
Step 4 .. 7458 8314
Step 5 .. 7452 8312

Of course, I would consider the new values a typo (is it?)... were it not for the oddity that both sets of values succeed in the June 2005 APU tests.

by blargg on 2006-10-24 (#18815)

Good catch. Since the fifth step in mode 1 doesn't do anything, there's no effect on a current APU emulator (7456+7454 = 7458+7452). Only when (if?) I ever work out the details of what happens when you restart/change modes within a couple of clocks of a step will this become relevant. The one/two clock delay after writing to $4017 before the mode begins is where the fun occurs. As I remember, you could for example switch from mode 1 to mode 0 just as mode 1 was doing a particular step and have it set the IRQ flag immediately if that step corresponded to the fourth step in mode 0. Don't try to implement this yet, because it's more complex than that. There's something really tedious about probing this because I never know how involved the behavior will be, "how far the rabbit hole will go".