Original question/context:
Per the below, MMC2 won't work. But having confirmed my sanity w/r/t registers, one MMC3 question:
What is loaded into $8000-$CFFF at power-on? Is $8000-$FFFF just the last 4 banks in the ROM (assuming a sane 128k/256k/512k footprint) or do I need to plan on an entry vector in the $E000+ range and bootstrap all the other swappable banks in by hand?
LoneKiltedNinja wrote:
Despite my various weird musical tech demos, I haven't worked directly with anything but mapper0 in ages.
I have a crazy notion for a project for which MMC2/mapper9 seems to be a perfect fit; I just want to confirm one detail:
Someone PLEASE tell me that the memory-mapped register behavior smearing 6 registers across the whole $A000-$FFFF space is only in the write direction. Because that would be sane. That would mean that the hardware basically uses the top 3 address bits of the write lines to mux to 6 writable regs while reads actually hit the fixed banks as documented ( http://wiki.nesdev.com/w/index.php/MMC2 ) and life is good and I don't need to get a MMC3 headache without nbasic asprin.
If, rather, you can use up to 128k of PRG so long as all execution at a given time fits within an 8k chunk that you're constantly swapping out from under yourself... to be fair, I could still FIND use cases, but just ow.
Am I sane? (or as sane as I can be contemplating "NES" and "Hatsune Miku" in the same sentence...) Or was the tech world mad in 1987 in a way that is likely to prove contagious by written exposure?
I have a crazy notion for a project for which MMC2/mapper9 seems to be a perfect fit; I just want to confirm one detail:
Someone PLEASE tell me that the memory-mapped register behavior smearing 6 registers across the whole $A000-$FFFF space is only in the write direction. Because that would be sane. That would mean that the hardware basically uses the top 3 address bits of the write lines to mux to 6 writable regs while reads actually hit the fixed banks as documented ( http://wiki.nesdev.com/w/index.php/MMC2 ) and life is good and I don't need to get a MMC3 headache without nbasic asprin.
If, rather, you can use up to 128k of PRG so long as all execution at a given time fits within an 8k chunk that you're constantly swapping out from under yourself... to be fair, I could still FIND use cases, but just ow.
Am I sane? (or as sane as I can be contemplating "NES" and "Hatsune Miku" in the same sentence...) Or was the tech world mad in 1987 in a way that is likely to prove contagious by written exposure?
Per the below, MMC2 won't work. But having confirmed my sanity w/r/t registers, one MMC3 question:
What is loaded into $8000-$CFFF at power-on? Is $8000-$FFFF just the last 4 banks in the ROM (assuming a sane 128k/256k/512k footprint) or do I need to plan on an entry vector in the $E000+ range and bootstrap all the other swappable banks in by hand?