I've been working on a project to build an SNES cart board from scratch (no special chips, MAD-1 decoder), and the one thing that I've been putting off for last is the MAD-1 decoder. I found neviksti's post in this thread
http://nesdev.com/bbs/viewtopic.php?t=4450&sid=0a852e0496df6c70188b08a7cfd8eec6 which gives me a really solid starting point, but I'm wondering, has anybody worked out a replacement for the MAD-1 (in both Lo and HiROM configurations) using in-production, off-the-shelf discrete logic parts? Neviksti's post should be more than enough information to get me an answer, but my combinatorial logic analysis is a bit rusty, and I figure it's better to ask first (well, better to search on my own first, which I have, then ask) to see if anybody has already worked it out before I try to do it myself...
This is what I came up with a long time ago (after analyzing the chip, not using documents), it looks accurate but no guarantees
Inputs:
Pin 9 is A
Pin 10 is B
Pin 11 is C
Pin 12 is D
Pin 13 is E
Pin 14 is F
Pin 15 is G
Outputs (active-low logic):
Pin 1 is G E C' A + E C' B A
Pin 2 is G F E D' C B A + G' F E D C' B' A + SRAMVCC' (pin 5)
Pin 3 is G F E' D' C B A + G' F' E D C' B' A
Pin 4 is G C' A + C' B A
Pin 16 is G E' C' A + E' C' B A
This is exactly what I have been working on and off for the last month.
I have much of the layout complete, but the MAD1 is the last piece of my puzzle as well.
This parts will work if you are using the battery method for saving.
I got a cart that is really copact (the pcb is smaller)
it uses these 3 chips a battery and a Nintendo D114X
the only thing is that it has an epoxy bubble on one side right where the D114x is.
here are the chips.
Here is the datasheet of the SONY chip
http://pdf1.alldatasheet.com/datasheet- ... 257AM.html
here is the data sheet of the Sanyo Chip
http://www.datasheets.org.uk/LE28DW3218 ... sheet.html
There is another smaller chip but the name of the maker doesnt seem to be there and it says
74HCt139D
http://www.datasheetcatalog.org/datashe ... _CNV_2.pdf
The Sanyo ROM appears to be discontinued, and I already have a better alternative in mind for SRAM (although it's a 3.3v part, so level shifting's gonna be a pain...). I'm also looking into Micron FlashROMs which, although they are also 3.3v parts, they have a significantly large x8/x16 parallel Flash ROM line that goes up to 2Gbit, so they're not likely to go anywhere in the near future (I really want to source all in-production parts, otherwise I'd just use 29F032's). A PIC12F629 works for the CIC key(SuperCIC key mode), and then I just need a decoder. The one you posted is just a dual 2-to-4 decoder, which IIRC was used in some SNES carts (not positive it was the -139, I get all those 74xx parts mixed up...), but I really need to look into it more before I decide on a decoder. Ideally, I'd really like a switchable decoder that can be simultaneously wired as HiROM and LoROM and easily switch between the two configurations, but I'm not sure how complicated that might be.
I have a feeling that the epoxy blob on your board is the decoder (in combination with the 139), so that board of yours is next to useless for design REing. My board will be significantly smaller than the official ones anyway due to smaller chips, the lack of a battery, and better PCB tolerances. Yes, I've seen that documentation. It doesn't help me nearly as much as kyuusaku's logic table. And no, I don't intend to implement that disgusting kludge they call a Lo/HiROM switch. That's the nice part about designing something from scratch, you have the freedom to do it right instead of hacking something together from existing designs.
oh ok, yeah well I guess I had no idea the chips on my board are obsolete.
but I thought am29f032s were discontinued too, and well if you use those i think your board might be a bit expensive.
I been working on this too,
and im stuck with the mapper.
Would looking into N64 carts help?
I know they saved on a flash memory.
No, N64 carts won't help. They use a much more interesting method of multiplexing the address and data lines which is entirely unlike the SNES. And yes, the 29F032's are obsolete as well, I was saying that if I were to use obsolete parts, that'd be my first choice. As it is, the Micron parts I'm looking at are around $2 each for the 32Mbit chip or about $3.50 for 64Mbit (or $4 for 128Mbit, if I REALLY feel like overdoing it; it'd only really useful for the Star Ocean NoSDD-1 hack). I need to sit down and combine all of what I know about the MAD-1 into a single, coherent document, most likely on paper (because paper just works better for me when I'm brainstorming), and then I'll see what I come up with in terms of the mapper. I'm planning on a single ROM chip and no SRAM battery, so that should simplify things a bit...
kyuusaku wrote:
Pin 3 is G F E' D' C B A + G' F' E D C' B' A
Are you sure on this? caitsith's documentation has pin 3 NC.
http://www.caitsith2.net/snes/flashcart/cart-chip-pinouts.html#mad
Well... I suppose that just because the pin isn't connected has no bearing on the logic for the pin, I just want to confirm the pin numbers.
"no guarantees", this was maybe 4 years ago.
I have no reason to believe it isn't correct... I dumped the logic manually using a binary counter in maybe 15 minutes so you could always verify it with a similar technique.
In this application there's absolutely no reason to implement the MAD-1 logic, just grab the Lo/HiROM SRAM decoding.
To support Lo/HiROM ROMs you need only some multiplexers to shift A[n:16] to A[n-1:A15].
I'm also trying to make my own PCB for HiROM, battery backup, 64 meg games and I use both 74LS138 and 74LS139 for address decoding.
To put SRAM into stand-by mode, I made a circuit with a NPN transistor and 2 diodes, and it seems to work fine.
would something like this work properly as a MAD-1 replacement? :
http://www.penguinet.net/TailChao/Extra ... /index.phpHe programmed a GAL16V8 chip as the memory/rom mapper and used an 8KB Ramtron FM1608 FRAM instead of the conventional MAD-1 and SRAM deal.
Seriously, I've tried half a dozen times to get the 16W08 to work on the SNES and I've never been able to >.< I'll have to ask him how he got it to work, because I've really been wanting to do that.
His method sounds promising, although the fram chip he uses is hard to find / expensive. On another tangent, I know that the old Mario Paint's used only a LS139 and another chip labeled D2145U to work the sram instead of Mad-1...maybe there is an alternative to whatever the D2145U is to control the sram state to make homebrew carts with sram+battery with a common '139?
I think magno mapped out that circuit. I don't see why it wouldnt work....
Magno, have you got a working schematic then for that battery+sram design you mentioned?
Here's a new direction.... Yoshi's island uses a small 8 pin chip for SRAM memory management with only 2 or 3 external components. The ones Nintendo used BA6129AF and the other is a MM1026AF.
I've sent an email to Maxim to see what the modern equivalent is. I'll keep you posted.
Then why didn't Nintendo use this method?
I'm not sure if two resistors and two diodes are enough to prevent stray writes as the CPU begins to lose power. I seem to remember Super NES games being engineered not to require the player to hold reset while turning power off.
tepples wrote:
I'm not sure if two resistors and two diodes are enough to prevent stray writes as the CPU begins to lose power. I seem to remember Super NES games being engineered not to require the player to hold reset while turning power off.
Vcc has to be greater than Vbattery for SRAM's /CE to be enabled by the MAD-1, so maybe this is enough to prevent issues during power down.
The carts do prevent issues during power up by connecting CE to /RESET on most MAD boards from what I understand.
getafixx wrote:
Magno, have you got a working schematic then for that battery+sram design you mentioned?
Yes, I have. Here it is:
Markfrizb wrote:
Yoshi's island uses a small 8 pin chip for SRAM memory management with only 2 or 3 external components. The ones Nintendo used BA6129AF and the other is a MM1026AF.
That component is outdated and you can't use it anyway: it controls SRAM's Vcc and /CS but paying attention only to Vcc. That means that, when Vcc drops below 3V, the chip MM1026AF detects the situation and triggers the low power mode: /CS = '1' and Vcc = 3.3V (it routes 3.3V from battery to SRAM Vcc). By doing it, you only can address 64K SRAM chips, since the address decoder would assert SRAM CS to activate/deactivate it. Besides this, there is another drawback: control logic is usually active low, so you will have to make "creative design" or use an inversor.
tepples wrote:
I'm not sure if two resistors and two diodes are enough to prevent stray writes as the CPU begins to lose power. I seem to remember Super NES games being engineered not to require the player to hold reset while turning power off.
I tell you: no, they are not enough. You must use a NPN transistor to properly assert SRAM /CS. However, diodes and resistors are enough to change between 5V and 3.3V while Vcc are dropping assuming /CS had been de-asserted by the NPN transistor prior to 5V fell below 3.3V.
Which address decoder output is this per your Schematic? Is it tied to any of the outputs or a specific one?