I think everyone's covered the details so far, but I'll say this:
Oziphantom wrote:
So I was trying to put Fire Emblem 4 into my Super Regenerator and I hit a few issues. Namely I didn't support HiROM yet, but as I added HiROM I still hit issues. The ROM is 8MB, and well HiROM only supports 6 apparently. Then I found for 8MB you need SA-1 ...
To be clear here: most mode 21 (HiROM) PCBs only support up to 32mbits (4MByte) of wired addressing space. Nintendo's own official documentation outlines this fact repeatedly throughout everything (from PCB documentation to memory map layouts later on in the same doc).
There
may be some unique PCBs that extend that to 48mbit (6MBytes) -- technically this is certainly possible depending on how the PCB is wired for extending the ROM-to-addressing space -- but they do not appear to be officially documented. (Nintendo, however, is known to have made some boards for specific developers (read: games) that are not officially documented but were in fact used for those games in final release. I do not know if this is relevant to the game you're looking at.)
For things larger than 32mbit (4MByte), you are expected to use mode 25 -- which supports up to 64mbit (8MByte) of addressing space. Mode 35 is just mode 25 but with high-speed (3.58MHz / fastROM) support. So what you're looking at is a mode 25 game. Sadly, Nintendo did not document production 64mbit boards in their docs (well, sort of; more on that in a moment.)
For development (read: PCBs supporting EPROMs natively), you're supposed to request an SHVC-8PV5B-64M board -- note the "-64M" part. However, in official documentation, refer to page 1-2-28 describing SHVC-8PV5B, and read the very fine print for some amusement: "The earlier 8PV5B PCB version can use up to 64mbit ROM, but do not exist 32mbit on this PCB (DSW1 pin 7 off)." In other words: some of the earlier developer PCBs allowed up to 64mbit "by chance" via extra traces that Nintendo later pulled for whatever reason. I believe this also applied to some production (mask ROM) PCBs.
An alternate approach is to use the SA-1 chip, which is a whole separate and unique beast of its own and will drive you absolutely insane. It is not "just a mapper" chip. If you ever encounter projects with this thing, my advice is to avoid them if you value your sanity.
So we're back to the question: what is the memory map for mode 25? The answer is actually on page 2-21-5 (figure 2-21-4), as you discovered. This diagram is "hard to understand" because of what all is mapped where non-linearly. lidnariq covered it tersely, but here's the mapping:
Bank $C0-FF, $0000-FFFF: first 32mbit of ROM -- supports fastROM / 3.58MHz
Bank $40-7D, $0000-FFFF: next 32mbit of ROM, sans the last 128KB of ROM (this is because of banks $7E-7F being the work RAM area)
Bank $3E-3F, $8000-FFFF: 64KB portion of the aforementioned 128KB of ROM -- not sure if the penultimate 64KB of ROM or the final/last 64KB; suspect penultimate. lidnariq, can you confirm/speculate?
And now for the mirroring (mirrored areas are denoted with a
' (apostrophe) after their description in the diagram; hard to see though):
Bank $00-3D, $8000-FFFF: upper half of banks $40-7D (this is needed for CPU vectors in bank $00, etc.
Bank $80-BF, $8000-FFFF: upper half of banks $C0-FF -- supports fastROM / 3.58MHz
And finally, battery-backed SRAM and DSP (don't know if this game has DSP or not, but SRAM almost certainly since it's an RPG):
Bank $00-0F, $6000-7FFF: DSP region (up to 128KB)
Bank $B0-BF, $6000-7FFF: battery-backed SRAM on cartridge (up to 128KB in size)
Hope this helps, and apologies if this confuses things at all.