Adding address line to cx4 board (32mb romhack)

I would really like to build myself a Zero Project 3.1 or Fully playable Zero MMX3 for my personal collection.
I know its doable, markfrizb have done it on a custom dev board.

The issue is its a 32mb romhack and 1DC0N and 2DC0N only supports 16mb.
I already tried using a 139 decoder with no success, only got a black screen.

Using a 139 decoder I wired /ce (cx4 pin 27) to decoder enabler
I used A21 (cx4 pin 15) as decoder input 1.
Vss as decoder input 2.
Decoder outputs where connected to maskrom1 /ce and maskrom2 /ce
I directly wired both maskrom A20 to cx4 pin34.

I've read lot of tech stuff about the cx4 here but cant recall what's wrong with my wiring
viewtopic.php?f=12&t=14647
viewtopic.php?f=12&t=10291

I dont want to build a fancy multicart with mix mapping and sram stuff, only a Zero MMX3 romhack.
I was hoping for some help. I have a 1DC0N and some 2DC0N PCB for testing.

I'll share results with you guys.
Thanks for the support.

The CX4 itself can only address 2 MiB when in lorom mode (plus native support for bankswitching in a 3rd megabyte by switching between the "one 2 MiB ROM" and "two 1 MiB ROMs" control register.

So whatever this ROM hack is doing, those extra 2 MiB have to be doing something different. I'd arbitrarily guess that there's a separate ROM that's there only for the SNES's CPU and the CX4 can't address.

Afaik, they're graphics relocated at the end of the ROM but apparantly it is possible to address 32Mbit on the Cx4 as seen here:
https://www.youtube.com/watch?v=UlMQPt2F4SQ


Just curious how. My guess would be tieing both EPROM /CE lines to GND and connect A20 to /CE1 and /CE2 of the Cx4, but I'm not sure. I've succesfully used one 27c160 by doing that on a 2DC0N board but that's it.

Just to briefly explain this:

There's a register ($7F52) in the CX4 that controls, when operating in LoROM layout, whether it expects one 2 MiB ROM, or two 1 MiB ROMs.

When the bit is set, ROM1 is enabled for all ROM access and ROMA20 is driven accordingly.
When the bit is clear, ROM2 is enabled when ROMA20 would have been high. (I don't know what A20 is doing at this time)

In this way, the software could bankswitch between 3 total MiB of stuff, but not more. And FPZ doesn't do this anyway.

That's probably why I'm having so much trouble emulating A21 with hardware.
Since its a MMX3 romhack and it normally uses 1DC0N.
Does it means that $7f52 is never set at $01???

Would it be possible in hirom mode instead?

Here is what I read:

As a plus, in HiROM mode it is possible to use 32MBits of cart ROM in two
16Mbit chips (by leaving $7f52 at $01), from E0:0000 onward the second ROM
will be selected.

In HiROM mode ROM is mapped as follows (assuming $7f52 = $01)

00-3F:8000-FFFF ROM1 0x100000-0x1FFFFF, ROM2 0x100000-0x1FFFFF
40-7D:0000-FFFF NOTHING (open bus with a bit of noise)
80-BF:8000-FFFF ROM1 0x100000-0x1FFFFF, ROM2 0x100000-0x1FFFFF
C0-FF:0000-7FFF ROM1 0x000000-0x0FFFFF, ROM2 0x000000-0x1FFFFF
C0-FF:8000-FFFF ROM1 0x100000-0x1FFFFF, ROM2 0x100000-0x1FFFFF

No, the FPZ rom hack is not using any of the features or misfeatures of the CX4.

My best guess is that the last 2 MiB are manually mapped into banks $40-$7D, but I really don't know.

The hack may not be compatible with the original Cx4 hardware. The implementation on the SD2SNES and in emulation might be able to support larger ROM sizes while the original can't. If only the S-CPU needs access to the additional ROM and not the Cx4 then you could make a circuit that would work if you prevent the Cx4 from responding to the address range that the new ROM data is mapped. However if the Cx4 needs to be able to access this data and the original chip can't address it then you're probably out of luck.

This isn't unusual because in the past many translations and ROM hacks were developed on emulators and later found out to not work on the real hardware.

The video Ice Man linked to above shows that youtube:arcademaster1 got it working on hardware.

I missed that. I bet you are correct though that the hack just expects the memory to be in those banks for the CPU and PPU to access. You just have to achieve that in hardware.

That would make sense since the last 2MB seem to be only graphics and possibly do not need the Cx4 at all and can be mapped like a normal LoROM game while the first 2MB should be connected to the Cx4.

Currently I'm using a 2DC0N pcb with two am29f016b eeprom and a 139 decoder for my test
So I'll need to make cx4 pin high. It seems on the pcb there is a pad especially for that, I'll give it a try.

But just to be sure before...
Do I need to make some modification to my rom file prior to those test?
Ie: converting it into hirom format using 32kb dummy file?
If so, they'll become 2x32mb eeprom.
No problem since I have some 29f033c.

I'm more a hardware guy, dont know a lot about rom mapping.
I've put the hirom info on my previous post, but sincerely, I dont know alot about it.

I think where on something guys, we'll make it together

Thanks again for the support

No, I'm about 90% certain you don't need to rewire the CX4 at all.

My best guess, given the video evidence and the CX4's memory map in LoROM mode is that you just need to enable the second ROM when the SNES's main CPU is trying to access banks $40-$7D and $C0-$FF.

Coincidentally, the $7f52 ROM selection is one of the few things still not emulated by my new Cx4 implementation in bsnes-plus (and the bizarre HiROM layout is another one). I guess I should probably consider doing so.

I think the bizarre HiROM layout is only a weird thing you need to emulate if you want to call the pins on the CX4 always the same thing regardless of how the mapping pin is strapped.

The same output pins always relay SNESA0-A14 and SNESA16-A19; the only difference is how those outputs are connected to the ROM's high address lines. The out-of-order-ness shown in qwertymodo's pinout (13 14 20 15 16) insinuates to me that the naïve map was intended to be HiROM and they did the simplest useful thing for LoROM compatibility.

Here is some update.
I've been able to have the rom to boot on the cartridge in lorom mode.
But when it load it shows interface register, immmediate register and immediate rom error.
When I try to lunch the game, the capcom logo and intro music starts.. then nothing... I get black screen, then a purple screen .

Here is how I wired my stuff.
First I used a FPZ rom hack that I splitted into 2x16mb
2xam29f016b eeprom and retrostage fx adapter
the eeprom /ce lines are connected to a 139 decoder.
Decoder enabler is vss and inputs are A21 (cx4 pin15) ans vss
Last I connected both eeprom A20 directly to the cx4 RA20 (pin34).

Here is a picture of my working board
Sorry about the fuzzy wiring, its kind of a test board, so I needed to have quick access to /oe, /cs, vss and vcc



Is the issue with the romhack or my build?
I think we are really close to it, a bit of help would be appreciated

Yeah, I didn't really intend to emulate it any differently than "normal" HiROM mapping, aside from the bank/ROM switching capability.

Your build

correct
Incorrect.

The CX4 in LoROM mode already relays data from the ROMs through the CX4 when /ROMSEL is low and A22 is low. (That's a 2 MiB region: A0 through A14 and A16 through A21 makes 21 address lines)

The remaining 2 MiB need to be directly connected to the data bus when /ROMSEL is low and A22 is high. It's still LoROM map, so you still need to ignore SNESA15.

Pardon my ignorance but how can I do that?

Changing my decoder input#1 I got different result

First I connected it to cart edge pin 46 (A21) and I got Interface, Register and Rom errors
Then I connected it to cart edge pin 47 (A22) and only got Register and Rom error.
I was able to boot the game a bit further, past the capcom logo. I got like 3 seconds of the intro scene, full music the the graphics frooze
Finally I connected the decoder input #1 to cart edge pin 48 (A23). Didnt get any error at startup but same thing, cant get to the title screen, still freeze during the intro scene.

Here is another build, a cleaner one so you may better understand how I'm testing it


How to I connect the remaining 2mb directly to the databus?
aka: the second eeprom?
I'm using a 139 decoder to control /ce lines of both eeprom, do I need to wire it differently?

Cant wait to get it working.
Thank you guys for the support

Sorry I didn't see the thread before. It got linked from here where I just posted what I did somewhere in 2016 to achieve what you're looking for. Funny to see how we pretty much went about it the same way.

Hi man, i've just pass this same issue with a megaman x2+x3 multicart on a rockman x2 donor. i just change the oscilator cristal rmx2 uses a 20mhz a change do 21,4 mhz and worked. i don't know why, but worked.