Earlier today someone pointed out some unintuitive behavior in my debugger when putting read breakpoints on the SMP bus, which led me to realize that a lot of SPC700 write instructions also perform a dummy read from the same address, like so:
Anomie's SPC cycle document describes the same behavior and mentions that it's been verified by blargg, which I trust.
But... what's the deal? Is it just a side effect of how the processor is designed, or does it have some actual purpose other than wasting cycles?
Code:
void SMPcore::op_mov_dp_const() {
rd = op_readpc();
dp = op_readpc();
op_readdp(dp); // ?????
op_writedp(dp, rd);
}
rd = op_readpc();
dp = op_readpc();
op_readdp(dp); // ?????
op_writedp(dp, rd);
}
Anomie's SPC cycle document describes the same behavior and mentions that it's been verified by blargg, which I trust.
But... what's the deal? Is it just a side effect of how the processor is designed, or does it have some actual purpose other than wasting cycles?