tepples wrote:
Given that the SPC700 is so similar to a 6502, why hasn't anybody written an SPC700 assembler that takes 6502 style mnemonics and spits out SPC700 object code?
You know, I can't imagine why I ever thought the SPC700 was based on a 6502. It might have a similar ALU, and they may have similar mnemonics for some of the opcodes, but other than that the instruction sets don't resemble each other at all.
I have a debug method in my code generation thingy that prints out a table. Here's the tables it prints for SPC700 and NMOS 6502:
Code:
SPC700InstructionSet:
{
NOP, CLRP, SETP, CLRC, SETC, EI, DI, CLRV, My addressing mode abbreviations
TCALL, TCALL, TCALL, TCALL, TCALL, TCALL, TCALL, TCALL, --------------------------------
SET1_d, SET1_d, SET1_d, SET1_d, SET1_d, SET1_d, SET1_d, SET1_d, m = Absolute
BBS_d_r, BBS_d_r, BBS_d_r, BBS_d_r, BBS_d_r, BBS_d_r, BBS_d_r, BBS_d_r, mx = Absolute Indexed X
OR_a_d, AND_a_d, EOR_a_d, CMP_a_d, ADC_a_d, SBC_a_d, MOV_d_a, MOV_a_d, my = Absolute Indexed Y
OR_a_m, AND_a_m, EOR_a_m, CMP_a_m, ADC_a_m, SBC_a_m, MOV_m_a, MOV_a_m, imm = Immediate
OR_a_ix, AND_a_ix, EOR_a_ix, CMP_a_ix, ADC_a_ix, SBC_a_ix, MOV_ix_a, MOV_a_ix, ix = X Indirect
OR_a_idx, AND_a_idx,EOR_a_idx,CMP_a_idx,ADC_a_idx,SBC_a_idx,MOV_idx_a,MOV_a_idx, ixi = X Indirect++
OR_a_imm, AND_a_imm,EOR_a_imm,CMP_a_imm,ADC_a_imm,SBC_a_imm,CMP_x_imm,MOV_a_imm, iy = Y Indirect
OR_d_d, AND_d_d, EOR_d_d, CMP_d_d, ADC_d_d, SBC_d_d, MOV_m_x, MOV_x_m, a = A
OR1_c_b, OR1_c_nb, AND1_c_b, AND1_c_nb,EOR1_c_b, MOV1_c_b, MOV1_b_c, NOT1_b, c = Carry flag
ASL_d, ROL_d, LSR_d, ROR_d, DEC_d, INC_d, MOV_d_y, MOV_y_d, p = PSW
ASL_m, ROL_m, LSR_m, ROR_m, DEC_m, INC_m, MOV_m_y, MOV_y_m, sp = SP
PUSH_p, PUSH_a, PUSH_x, PUSH_y, MOV_y_imm,CMP_y_imm,MOV_x_imm,NOTC, x = X
TSET1_m, CBNE_d_r, TCLR1_m, DBNZ_d_r, POP_p, POP_a, POP_x, POP_y, y = Y
BRK, BRA_r, PCALL, RET, MOV_d_imm,MOV_ixi_a,MUL_ya, SLEEP, ya = YA
BPL_r, BMI_r, BVC_r, BVS_r, BCC_r, BCS_r, BNE_r, BEQ_r, imx = JMP Absolute Indexed Indirect
TCALL, TCALL, TCALL, TCALL, TCALL, TCALL, TCALL, TCALL, idx = Direct Indexed X (RMW)
CLR1_d, CLR1_d, CLR1_d, CLR1_d, CLR1_d, CLR1_d, CLR1_d, CLR1_d, diy = Direct
BBC_d_r, BBC_d_r, BBC_d_r, BBC_d_r, BBC_d_r, BBC_d_r, BBC_d_r, BBC_d_r, d = Direct
OR_a_dx, AND_a_dx, EOR_a_dx, CMP_a_dx, ADC_a_dx, SBC_a_dx, MOV_dx_a, MOV_a_dx, dx = Direct Indexed X
OR_a_mx, AND_a_mx, EOR_a_mx, CMP_a_mx, ADC_a_mx, SBC_a_mx, MOV_mx_a, MOV_a_mx, dy = Direct Indexed Y
OR_a_my, AND_a_my, EOR_a_my, CMP_a_my, ADC_a_my, SBC_a_my, MOV_my_a, MOV_a_my, d = Test-and-Branch Direct
OR_a_diy, AND_a_diy,EOR_a_diy,CMP_a_diy,ADC_a_diy,SBC_a_diy,MOV_diy_a,MOV_a_diy, d = Direct Destination (d_d)
OR_d_imm, AND_d_imm,EOR_d_imm,CMP_d_imm,ADC_d_imm,SBC_d_imm,MOV_d_x, MOV_x_d, d = Direct Source (d_d)
OR_ix_iy, AND_ix_iy,EOR_ix_iy,CMP_ix_iy,ADC_ix_iy,SBC_ix_iy,MOV_dy_x, MOV_x_dy, nb = MemBit
DECW_d, INCW_d, CMPW_ya_d,ADDW_ya_d,SUBW_ya_d,MOVW_ya_d,MOVW_d_ya,MOV_d_d, b = MemBit
ASL_dx, ROL_dx, LSR_dx, ROR_dx, DEC_dx, INC_dx, MOV_dx_y, MOV_y_dx, r = PC relative
ASL_a, ROL_a, LSR_a, ROR_a, DEC_a, INC_a, DEC_y, INC_y, impl = implied
DEC_x, INC_x, MOV_x_a, MOV_a_x, MOV_x_sp, MOV_sp_x, MOV_a_y, MOV_y_a,
CMP_x_m, CMP_x_d, CMP_y_m, CMP_y_d, DIV_ya_x, DAS_a, CBNE_dx_r,DBNZ_y_r,
JMP_imx, CALL_m, JMP_m, RET1, XCN_a, MOV_a_ixi,DAA_a, STOP,
}
N6502InstructionSet:
{
BRK, JSR_a, RTI, RTS, SKB_imm, LDY_imm, CPY_imm, CPX_imm, My addressing mode abbreviations
ORA_dxi, AND_dxi, EOR_dxi, ADC_dxi, STA_dxi, LDA_dxi, CMP_dxi, SBC_dxi, --------------------------------
HLT, HLT, HLT, HLT, SKB_imm, LDX_imm, SKB_imm, SKB_imm, diy = (Indirect),Y
SLO_dxi, RLA_dxi, SRE_dxi, RRA_dxi, SAX_dxi, LAX_dxi, DCP_dxi, ISC_dxi, dxi = (Indirect,X)
SKB_d, BIT_d, SKB_d, SKB_d, STY_d, LDY_d, CPY_d, CPX_d, a = Absolute
ORA_d, AND_d, EOR_d, ADC_d, STA_d, LDA_d, CMP_d, SBC_d, ax = Absolute,X
ASL_d, ROL_d, LSR_d, ROR_d, STX_d, LDX_d, DEC_d, INC_d, ay = Absolute,Y
SLO_d, RLA_d, SRE_d, RRA_d, SAX_d, LAX_d, DCP_d, ISC_d, acc = Accumulator
PHP, PLP, PHA, PLA, DEY, TAY, INY, INX, imm = Immediate
ORA_imm, AND_imm, EOR_imm, ADC_imm, SKB_imm, LDA_imm, CMP_imm, SBC_imm, impl = Implied
ASL_acc, ROL_acc, LSR_acc, ROR_acc, TXA, TAX, DEX, NOP, ai = Indirect
ANC_imm, ANC_imm, ALR_imm, ARR_imm, XAA_imm, OAL_imm, LXA_imm, SBC_imm, pcr = Relative
SKW_a, BIT_a, JMP_a, JMP_ai, STY_a, LDY_a, CPY_a, CPX_a, d = Zero Page
ORA_a, AND_a, EOR_a, ADC_a, STA_a, LDA_a, CMP_a, SBC_a, dx = Zero Page,X
ASL_a, ROL_a, LSR_a, ROR_a, STX_a, LDX_a, DEC_a, INC_a, dy = Zero Page,Y
SLO_a, RLA_a, SRE_a, RRA_a, SAX_a, LAX_a, DCP_a, ISC_a,
BPL_pcr, BMI_pcr, BVC_pcr, BVS_pcr, BCC_pcr, BCS_pcr, BNE_pcr, BEQ_pcr,
ORA_diy, AND_diy, EOR_diy, ADC_diy, STA_diy, LDA_diy, CMP_diy, SBC_diy,
HLT, HLT, HLT, HLT, HLT, HLT, HLT, HLT,
SLO_diy, RLA_diy, SRE_diy, RRA_diy, SHA_diy, LAX_diy, DCP_diy, ISC_diy,
SKB_dx, SKB_dx, SKB_dx, SKB_dx, STY_dx, LDY_dx, SKB_dx, SKB_dx,
ORA_dx, AND_dx, EOR_dx, ADC_dx, STA_dx, LDA_dx, CMP_dx, SBC_dx,
ASL_dx, ROL_dx, LSR_dx, ROR_dx, STX_dy, LDX_dy, DEC_dx, INC_dx,
SLO_dx, RLA_dx, SRE_dx, RRA_dx, SAX_dy, LAX_dy, DCP_dx, ISC_dx,
CLC, SEC, CLI, SEI, TYA, CLV, CLD, SED,
ORA_ay, AND_ay, EOR_ay, ADC_ay, STA_ay, LDA_ay, CMP_ay, SBC_ay,
NOP, NOP, NOP, NOP, TXS, TSX, NOP, NOP,
SLO_ay, RLA_ay, SRE_ay, RRA_ay, SHS_ay, LAS_ay, DCP_ay, ISC_ay,
SKW_ax, SKW_ax, SKW_ax, SKW_ax, SHY_ax, LDY_ax, SKW_ax, SKW_ax,
ORA_ax, AND_ax, EOR_ax, ADC_ax, STA_ax, LDA_ax, CMP_ax, SBC_ax,
ASL_ax, ROL_ax, LSR_ax, ROR_ax, SHX_ay, LDX_ay, DEC_ax, INC_ax,
SLO_ax, RLA_ax, SRE_ax, RRA_ax, SHA_ay, LAX_ay, DCP_ax, ISC_ax,
}
Edit: added lists of what my addressing mode abbreviations mean on the right. (need a wide monitor, sorry)
The branch instructions are in the same place? Not much else is.