Blargg or any experts in SPC700, TSET1 TCLR1 instruction ?

I am writing a SNES emulator trying to be clock correct, and I am working on the APU part.
I want to test my SPC700 implementation and I have come across this thread of this forum

http://forums.nesdev.com/viewtopic.php?f=12&t=10697


This thread points to a testing suite developed by Blargg :

spc-700-cpu-tests.zip


I downloaded it and port the 12 test programs to my design.
10 of them passed and two of them failed.
The 2 failed are :
CPU Instructions_Edge_arith
CPU_tset tclr

I am very grateful to have these programs to test my implementation.
I am still looking in the Instructions_Edge_arith and will report or fix my implementation.

However, when I study why CPU_tset tclr fail, I found out the following

1. This test seems to test 5 sets of data on the two instructions TSET1 and TCLR1
2. The instruction of TSET1 and TCLR1 are


mnemoic address_mode opcode byte cycle flag affected Description
TSET1 !abs 0E 3 6 N-----Z- Test and set bits with A ( mem.byte |= ACC, set the active bits ) {OpCode,addr_L,addr_H}
TCLR1 !abs 4E 3 6 N-----Z- Test and clear bits with A ( mem.byte &= ~ACC, clear the active bits ) {OpCode,addr_L,addr_H}

3. The five sets of data being test are, the last two columns are my guess, I include the result of RAM_$E1 to further elaborate, such that ( Reg_A, PSW, result_RAM_$E1 )

________Reg_A_____RAM_$E1________TSET1 result ( Reg_A, PSW ) ___ TCLR1 result ( Reg_A, PSW )____ TSET1_my_guess______ TCLR1
3.1_____ 0x00______ 0x00_______________0x00, 0x02___________________ 0x00, 0x02_________________0x00, 0x02, 0x00 ____ 0x00, 0x02, 0x00
3.2_____ 0x00______ 0x01_______________0x00, 0x80___________________ 0x00, 0x80_________________0x00, 0x00, 0x01 ____ 0x00, 0x00, 0x01
3.3_____ 0x01______ 0x00_______________0x01, 0x00___________________ 0x01, 0x00_________________0x01, 0x00, 0x01 ____ 0x01, 0x02, 0x00
3.4_____ 0x01______ 0x01_______________0x01, 0x02___________________ 0x01, 0x02_________________0x01, 0x00, 0x01 ____ 0x01, 0x02, 0x00
3.5_____ 0x00______ 0xFF_______________0x00, 0x00___________________ 0x00, 0x00_________________0x00, 0x80, 0xFF ____ 0x00, 0x80, 0xFF

I don't have a traceable hardware to verify the above, however, I found difference in the description and the flags

In fact running this two instructions TSET1,TCLR1 with Reg_A is 0x00 should have very little effect

for 3.1, it seems OK
for 3.2, This is because the N bit (bit7) of RAM_$E1 should not be set by these two instructions, so both should be off
for 3.3 TCLR1 should set the Z flag because result is zero
for 3.4 TSET1 sets a bit already on, TCLR1 clear the bit that is on to off, so result is again zero
for 3.5 Since the result is negative, the N bit should be set.

I am not sure what went wrong or if that is really the PSW. Because the PSW seems completely unrelated to the result at $00E1 location

Furthermore, the PSW is valid if it is the result of the equation : signed subtract of ( Reg_A - $00E1 )
however, this does not make sense as this is suppose to be a logical instruction not an arithmetic instruction

Thanks for reading and best regards

Sorry it seems to remove all my extra spaces. Can anyone teach me how to put in the spaces to facilitate easier readin ?

The [code] tag preserves extra spaces.

Oh.. I found out in the GitHub document in one sentence that it states

the flags are actually derived from

A - (a)

and these bits has no relationship to the actual result byte. ( This is wierd and should be a bug of the original SPC700 )


I had adjusted my code and now it also pass Blargg test.


Thanks Blargg

Glad to report that all test now pass. I had make a typo in the AND1 C,/mem,bit instruction that cause failure in the CPU edge test.
It is now resolved.