In anomie's apudsp.txt it states:
I understand the frequencies at which the 3 timers tick and why I'm ticking T2 twice every 32 clock cycles and T0/T1 only once every 4 samples. No problem there.
However, one part confuses me. The doc seems to be stating that immediately out of reset in SMP clock cycle 0 that the stage 1 timers should tick. This seems a bit weird from a hardware design perspective because it seems more likely that the stage 1 timers wouldn't produce their very first tick until either 15.625us have passed (for T2) or 125us have passed (for T0/T1). If it ticks immediately out of reset then it is essentially producing ticks before any time has passed at all.
I can implement it either way but I just want to be sure that I'm understanding it right before I go changing my code. Right now I have it where the first ticks don't happen until 15.625us or 125us have passed. In other words, my stage 1 timer is a simple up counter that counts the appropriate number of clock cycles and then "ticks". So my stage 1 timer would never tick immediately out of reset - instead there would be an appropriate delay before the first tick. Is that incorrect behavior?
apudsp.txt wrote:
0. Voice steps: 0:V5 1:V2
Tick the SPC700 Stage 1 timers, always for T2 and every 4 samples for
T0 and T1.
Tick the SPC700 Stage 1 timers, always for T2 and every 4 samples for
T0 and T1.
I understand the frequencies at which the 3 timers tick and why I'm ticking T2 twice every 32 clock cycles and T0/T1 only once every 4 samples. No problem there.
However, one part confuses me. The doc seems to be stating that immediately out of reset in SMP clock cycle 0 that the stage 1 timers should tick. This seems a bit weird from a hardware design perspective because it seems more likely that the stage 1 timers wouldn't produce their very first tick until either 15.625us have passed (for T2) or 125us have passed (for T0/T1). If it ticks immediately out of reset then it is essentially producing ticks before any time has passed at all.
I can implement it either way but I just want to be sure that I'm understanding it right before I go changing my code. Right now I have it where the first ticks don't happen until 15.625us or 125us have passed. In other words, my stage 1 timer is a simple up counter that counts the appropriate number of clock cycles and then "ticks". So my stage 1 timer would never tick immediately out of reset - instead there would be an appropriate delay before the first tick. Is that incorrect behavior?