I've reached the final stage of the Cx4 dev cart I've been playing around with on and off the last few months, but I've hit a wall right at the end that has me completely stumped. Reading works fine, but trying to write to the ROM via the cart edge doesn't seem to be working. First of all, the ROM /CE line is not asserted low for writes to the ROM address space, but I've determined that pin 51 appears to be a /WR output from the Cx4 (it tracks the cart edge /WR signal in all of my tests, including writes to the ROM address space, but I haven't checked it out with an oscilloscope to know any better than that). So, to handle that, I cut the /CE signal to the ROM, and am decoding it as /WR_OUT AND /CE_OUT (the pin on the Cx4 that it was previously connected to), which maintains read functionality, but still doesn't work for writes. I hooked up my logic analyzer, and everything looks like it's working. I've attached screenshots of the logic analyzer output. I'm limited to 8 channels, so I ran the same operation 3 times so I could display the control lines as well as A[3:0], D[3:0], and D[7:4], respectively. The only strange behavior is the short high spike on the data lines immediately following the control lines going low, but that shouldn't be a problem, since the only time that the data lines need to be valid is during the *rising* edge of /CE or /WE, whichever comes first (the order doesn't matter). Timing looks well within spec, I really don't understand what's going on... any ideas?
Here's the chip datasheet
The operation shown in the screenshots is an attempt to execute the erase command (datasheet page 47):
All of the signals in the logic analyzer screenshots are directly tapped from pins on the ROM, except for /CS_OUT, which is pin 52 on the Cx4. To my eye, the write cycles look good... not really sure what's going on
Here's the chip datasheet
The operation shown in the screenshots is an attempt to execute the erase command (datasheet page 47):
Code:
ROMWriteByte(0xAAA, 0xAA);
ROMWriteByte(0x555, 0x55);
ROMWriteByte(0xAAA, 0x80);
ROMWriteByte(0xAAA, 0xAA);
ROMWriteByte(0x555, 0x55);
ROMWriteByte(0xAAA, 0x10);
while(ROMReadByte(0x0000) != 0xFF);
ROMWriteByte(0x555, 0x55);
ROMWriteByte(0xAAA, 0x80);
ROMWriteByte(0xAAA, 0xAA);
ROMWriteByte(0x555, 0x55);
ROMWriteByte(0xAAA, 0x10);
while(ROMReadByte(0x0000) != 0xFF);
All of the signals in the logic analyzer screenshots are directly tapped from pins on the ROM, except for /CS_OUT, which is pin 52 on the Cx4. To my eye, the write cycles look good... not really sure what's going on