If SNES CPU is 16-bit, why is Cart data bus 8bit wide?

I am wondering this as I learn more about micro processors etc.

I am not clear how a xx-bit CPU relates to the width of the data bus.

I am wondering is the 65816 somehow 16-bit, although the data bus are 8 bit. Is that unique to 65816.

Please lecture me on processors.

i figured it out. datasheet ftw
http://www.jameco.com/Jameco/Products/P ... 143662.pdf

page 10 shows the internal 16-bit databus. That's enough for me.

♪ Genesis does ♪
16-bit data bus
♪ You can't do this on Nintendo ♪♪

A lot of Nintendo consoles have narrow data buses.
Super NES: Every data bus on the motherboard is 8-bit
Nintendo 64: 8-bit (or 9-bit?) bus to RAM at a very high clock rate
GBA: Memory (except for the BIOS and 32 KiB of IWRAM) is 16-bit with no cache. Most 32-bit operations are wait state city.
GameCube: A-RAM is 8-bit (source) and has such low bandwidth to the rest of the system that the part not used by the audio chip was most often used as a disc cache.
Nintendo DS: 16-bit RAM (cached, fortunately) and 8-bit bus to the Game Card

8bit bus saves quite some money, let less PCB realestate, less IO used so smaller cheaper packages... but you have half the bandwidth, unless clock is pushed twice as high which is not always an option. That is why oldass PCI GFX cards have 64 or 128bit DRAM buses, to move a ton of data within available clock speeds.

The ALU is 16bit and that is what makes up the bitness. I recently read the Z80 has a 4bit ALU, technically it 4bits, even though it cannot do any 4bit operations (maybe BCD squeezes in some way...) and can do some 16bit stuff too.

On 68000, it was an option. Like the Z80, the 68000 accesses memory only once every four cycles, allowing it to share unified memory with other devices on the bus. So just as with the Z80 compared to the 6502, you need to clock 68000 twice as fast to keep the same memory bandwidth.

Z80 has 4 cycles only for instruction fetches, and only because it pushes a refresh cycle in, other accesses are 3 cycles long, 1 cycle of them is also for sampling the !WAIT signal.
On 68K all bus accesses are 4 cycles unless !DTACK assertion is extended, then the access is extended until !DTACK is deasserted.
The bus is driven during all those cycles, if you want to use "dead" cycles you need bus switches.

The original 8088 also had an 8-bit data bus and was a 16-bit CPU.
(The 8086 had the 16-bit data bus. The 68000, 80386SX, and 80486SLC2 had 16-bit busses but were 32-bit CPUs. The 68008 even had an 8-bit data bus but was a 32-bit CPU)
Pin count is usually the most expensive thing in ICs, and it is a trivial cost reduction that can be made after the design has been finalized, so if it made sense to offer a pin-reduced version, manufacturers often did.)

Hence Apple's use of DE9 and later mini-DIN-8 serial ports for printers when the rest of the world was using DB25 parallel ports. But parallel ports exist for a reason: sometimes frequency is limited. Expansion from 1 to 4 bits per cycle is why the SD memory card format added extra data pins compared to the SPI-style MMC it was based on.