As I tried to figure out the nitty-gritty of PPU Addressing in my last post, I thought I would try my hand with CPU Addressing in this post. The external memory map areas are CPU RAM $0000-#1FFF, $4018-$5FFF, WRAM $6000-7FFF, and PRG ROM $8000-$FFFF. Much of these addresses are decoded by the 74HC139. Address lines A0-A14 go to the cartridge, allowing for 32KB of memory at first blush. This would put the PRG ROM at $0000-$7FFF. This would not do, so A15 is fed into one of the inputs of the '139, and M2 is fed into the other. When both are high, then the output pin connected to the /CS of the PRG ROM inside the cartridge is low and the ROM is enabled, at least until M2 falls. I don't understand the need for M2.
Now, to continue our digression. The CPU RAM is connected fully and directly to the CPU's address bus. Its /CS is tied to anohter pin of the '139. When M2 is high and A15 is low, one of the pins becomes low and activates the other decoder. The inputs of this decoder are attached to A13 and A14. When both address lines are low, then an output pin activates the /CS and enables the CPU RAM. This signifies a value in the $0000-$1FFF range. (In this state A11 and A12 would be unattached, which causes the CPU RAM to be repeated.) Interestingly, when A13 is high and A14 is low, another output pin goes to the PPU, which is in the $2000-$3FFF range.
Now, for WRAM inside the cartridge, things become a bit trickier. In order for the WRAM to appear at the right place, A13 and A14 must be high while A15 low. An 8KB chip only has A0-A12 connected, so its /CE must be enabled through inversion. Fortunately, when A15 is low, the PRG ROM is disabled, which avoids bus conflicts. A '139 would do the trick if the PRG CS line is inverted and used as the enable.
That just leaves $4018-$5FFF. Obviously, the NES CPU could have mirrored the APU, Sprite and I/O registers across this space, but it did not. This area seems to be just a big hole which the odd size made it too complex for your average mapper. Apparently Namco didn't see it that way with its 106 mapper, nor did Kevtris in his CopyNES.
Now, to continue our digression. The CPU RAM is connected fully and directly to the CPU's address bus. Its /CS is tied to anohter pin of the '139. When M2 is high and A15 is low, one of the pins becomes low and activates the other decoder. The inputs of this decoder are attached to A13 and A14. When both address lines are low, then an output pin activates the /CS and enables the CPU RAM. This signifies a value in the $0000-$1FFF range. (In this state A11 and A12 would be unattached, which causes the CPU RAM to be repeated.) Interestingly, when A13 is high and A14 is low, another output pin goes to the PPU, which is in the $2000-$3FFF range.
Now, for WRAM inside the cartridge, things become a bit trickier. In order for the WRAM to appear at the right place, A13 and A14 must be high while A15 low. An 8KB chip only has A0-A12 connected, so its /CE must be enabled through inversion. Fortunately, when A15 is low, the PRG ROM is disabled, which avoids bus conflicts. A '139 would do the trick if the PRG CS line is inverted and used as the enable.
That just leaves $4018-$5FFF. Obviously, the NES CPU could have mirrored the APU, Sprite and I/O registers across this space, but it did not. This area seems to be just a big hole which the odd size made it too complex for your average mapper. Apparently Namco didn't see it that way with its 106 mapper, nor did Kevtris in his CopyNES.