I am trying to determine exactly how the PPU maps the CHR ROM/CHR RAM into $0000-$1FFF and the VRAM into $2000-&3F00. I know that the CHR ROM or CHR RAM, which is a maximum of 8KB without bankswitching, is mapped into $0000-$1FFF, which is an 8KB addressing space. CHR ROM holds the pattern table, the actual graphics characters that are displayed on the screen. I also know that the 2KB VRAM inside the NES is mapped to the $2000-$2FFF area, and cartridge mirroring through the VRAM's A10 line controls which of the four $400 portions of that space are unique. This portion of memory holds the name tables, which are pointers to the pattern tables in the CHR ROM/RAM, and the attribute tables, which provide color for a set of tiles. I am also aware that the VRAM is mirrored in the $3000-$3F00 area, and after that comes $20 bytes of of palette memory, which is internal to the PPU and is mirrored for the rest of the page.
Now that I have mastered the basics, I need to know how the PPU knows that the CHR ROM and the VRAM should be in the above described places. The CHR ROM connects to A0-A12. The VRAM is connected to A0-A9, and sometimes A10 or A11. This should put the two memories in the same place, but it does not apparently due to the behavior of the A13 line. Now, if you only have 13 address bits, the maximum amount of memory you can address is $2000. It takes a 14th bit to go beyond that. This must mean that when the PPU is reading from the CHR ROM/RAM, A13 must be 0. The opposite must be true for a read from the VRAM, A13 must be 1.
Now, according to the schematics I have seen, it seems as though the opposite is true. A13 is inverted and connected to the CS of the CHR ROM/RAM, and A13 (uninverted) is almost always connected to the CS of the VRAM. Both CS signals are active low. This would mean that when A13 is logically high (1), then the VRAM chip is disabled and not on the bus. Also, when A13 is logically low, it is inverted to a high signal and causes the CHR ROM/RAM chip to be disabled. What am I missing?
Now that I have mastered the basics, I need to know how the PPU knows that the CHR ROM and the VRAM should be in the above described places. The CHR ROM connects to A0-A12. The VRAM is connected to A0-A9, and sometimes A10 or A11. This should put the two memories in the same place, but it does not apparently due to the behavior of the A13 line. Now, if you only have 13 address bits, the maximum amount of memory you can address is $2000. It takes a 14th bit to go beyond that. This must mean that when the PPU is reading from the CHR ROM/RAM, A13 must be 0. The opposite must be true for a read from the VRAM, A13 must be 1.
Now, according to the schematics I have seen, it seems as though the opposite is true. A13 is inverted and connected to the CS of the CHR ROM/RAM, and A13 (uninverted) is almost always connected to the CS of the VRAM. Both CS signals are active low. This would mean that when A13 is logically high (1), then the VRAM chip is disabled and not on the bus. Also, when A13 is logically low, it is inverted to a high signal and causes the CHR ROM/RAM chip to be disabled. What am I missing?