Hi!
I have some questions about the save RAM.
save RAM shares same address lines (A0 - A14) with PRG-ROM, so
when writing to $6000 (save RAM) $8000 (PRG-ROM) is disabled by
ANDing M2 with A15, save RAM is disabled with same fashion by
ANDing A14 with A13.
Where exactly save RAM /OE and /WE (from memory chip) are
connected physically? Should i connect /WE to PRG R/W?
I'm assume that /CE (chip enable) can be enabled by NANDing
A13 with A14.
Do i need a mapper for writing to save RAM? NES schematics suggests
that i don't need a mapper for reading.
What exactly is M2? in NES schematics it's marked as "O2",
should i see it as a somekind of address line enabler?
and for what purpose it's present at the cart connector?
Thank you
- Sepi
M2 or Phi2 is one of the clock signals on the NES board.
I found a document that stated that M2 is actually the main CLK ~21MHz
divided by 12, and all memory access is done when M2 is high.
Just for curiosity, where does abbreviation M2 or Phi2 come from?
- Sepi
It uses Phi, the greek letter, in the 6502 datasheet. I'm not sure where the M comes from.
The address decoding sounds about right. But you need to include M2 in the chip enables. You can use the PRG /CE pin, which is A15 NAND M2. If PRG /CE, M2, A13, and A14 are all high, you can enable the WRAM. My cart does this with a NAND gate and a 2-to-4 line decoder.
For the WRAM /WR and /RD signal, I hooked PRG R/W directly up to /WR. And inverted it for the /RD (with another NAND gate).
Yes, it all pretty clear now, my NVRAM chip has /CE and /OE and /WR.
It looks like i'll have to use a different chip because the one i have now
requires /OE to be high and /CE low during the write cycle, RAM chips
don't care about /OE.
Actually that particular NVRAM chip is designed for EEPROM replacement,
no wonder it cannot replace RAM chip.
Thank you very much!
- Sepi
Actually, I mis-spoke earlier. I meant to type that I hooked the inverted PRG R/W signal to the WRAM's /OE. I was thinking of it as a /RD signal, since it is required to do a read. Having /OE and /WR low at the same time would not be good (but maybe some chips would give priority to one or the other).
The NVRAM you have sounds normal from what I can tell.
Hmm, i checked some RAM datasheets if remember correctly,
RAM chip don't care about /OE at all, they perform the write cycle
if /CE and /WE are low, and completed when /CE or /WE goes high.
NVRAM that i have requires that /OE must be held high before
writing to it. In other words /OE is never considered as X (don't care)
with NVrAM it's easier to generate a bus conflict.
I can't guarantee that this information is accurate.
- Sepi
Still sounds to me like normal SRAM procedure, unless I'm confused. If PRG R/W was inverted and fed to the RAM's /OE, then /OE will always be high whenever /WE is low.
(off-topic warning)
Good to see you again, BTW. I haven't talked to you for a while. It's kinda funny how I finally implementing that NES-to-PC comms stuff. Using a PIC's UART on a cart, I ended up getting the convenience of parallel writes with the simplicity of serial hardware.
I checked it from the datasheet, you're right there wasn't anything
strange about the NVRAM write cycle, keeping /OE inactive was more
a recommendation, /WE automatically disables output drives when
/WE is active. In a event that there is more than one device accesing
the same RAM chip it's possible to generate a bus conflict but in NES this
never happens with $6000 unless you're doing something crazy with it.
<off-topic>
Well, it nice to know that it finally works! You know, when we were
developing that parallel port version, the information we needed
wasn't covered in any NES document out there, and also i finally
made that NES movie player/recorder by implementing that interrupt
server it was about zillion times more accurate than the VB version.
- Sepi