thefox wrote:
The multiple memory accesses made by the same instruction may also have completely unrelated addresses (to what you want to do). For example, if X = $AB and the instruction LDA $4567,X is executed, the first read will happen at address $4512 and the second one at $4612.
This is the first I've heard of this behaviour with absolute indexed-X addressing. I was under the impression there was only one read done (to the final calculated absolute 16-bit address, $4612 in this example), regardless if there was a page wrap or not.Edit: Because I can't make heads or tails of the stuff on visual6502.org (too low-level and not "concise" enough for me), I found
this, subsection 2.5, the breakdown is listed (with some reformatting done by me, focusing solely on abs,x addressing):
Code:
Tn Address Bus Data Bus R/W Comments
T0 PC OP CODE 1 Fetch OP CODE
T1 PC + 1 BAL 1 Fetch low order byte of Base Address
T2 PC + 2 BAH 1 Fetch high order byte of Base Address
T3 ADL: BAL + X Data* 1 Fetch data (no page crossing)
ADH: BAH + C Carry is 0 or 1 as required from previous add operation
T4* ADL: BAL + X Data 1 Fetch data from next page
ADH: BAH + 1
* If the page boundary is crossed in the indexing operation, the data fetched in T3 is ignored.
If page boundary is not crossed, the T4 cycle is bypassed.
I've been sitting here for the past 15 minutes reading this explanation over and over and over and I could interpret it in multiple ways. The part I'm having trouble understanding is why for T3 it says "ADH: BAH + C", where C is the carry result (0 or 1) of the previous BAL+X addition (in other words, if BAL+X results in a page wrap, it would be BAH+1, otherwise it's BAH+0). To me, that would indicate that truly only 1 data read operation would be required.
If the text for T3 said "ADH: BAH" and not "ADH: BAH + C" then it'd be more clear to me why there were two reads (one from
$4512 and then another from
$4612).
But then again my own questioning is refuted because it's quite clear for a page-wrapped index operation (like in the example given,
lda $4567,x where
X=$ab), there are in fact two data reads done by the CPU (in T3 and then again in T4).